Improved device performance and increased circuit density have been long-lasting goals of the integrated circuit industry. More specifically, for metal oxide semiconductor (MOS) field effect transistors (FETs), which are hereafter generalized as FETs, the industry has tried to improve device performance in many ways, such as: (1) increasing device electrical isolation; (2) reducing leakage current; (3) reducing capacitance to increase device switching speed and therefore improved the speed of operation; (4) improving device lifetime; (5) improving device current carrying capability; (6) reducing short channel behavior; (7) increasing circuit density; (8) reducing threshold voltage (Vt) shifts; and (9) reducing device dimensions.
To improve semiconductor devices, in some of the areas mentioned above, the industry began researching semiconductors on three-dimensional structures, such as vertical transistors. Most successful vertical transistor technologies involve the growth or deposition of a thin region of semiconductor material, such as silicon, for use as a FET channel and in some cases for use as a source region and a drain region. The channel is contained by dielectrics having perimeters requiring isolation and is placed adjacent to the source region and the drain region. The source and drain regions are always a conductive or semiconductive material to allow for FET current flow and device operation.
Another process technology, known as epitaxial growth, has been studied and used to improve the performance of semiconductor devices. Epitaxial growth is a crucial step for most vertical transistor processes. Epitaxy, when interpreted literally means "arranged upon," in a more relevant manner is the growth on a crystalline substrate of a crystalline substance that copies the orientation of the substrate.
The combination of vertical transistor technology and silicon epitaxial growth has produced devices, such as complex three-dimensional devices and surrounding gate devices, that have enhanced capability or performance. An example of a performance improving structure is the surrounding gate transistor (SGT). The SGT structure is a vertical stacked transistor with a conductive gate that surrounds a vertical semiconductor channel region. The SGT improved transistor performance in many of the ways listed above but had a few disadvantages. The SGT structure, as well as all other known and complex vertical epitaxially formed transistor structures, have the disadvantages of: (1) the gate, source and drain are difficult to make contact to with overlying conductive layers, such as metal layers; (2) a gate polysilicon bottom electrode prevents the impurity doping of the source and the drain; and (3) the SGT device is not capable of dimension reduction into smaller submicron ranges due to contact problems.